Projects / DOLPHIN SMASH

DOLPHIN SMASH

DOLPHIN SMASH is a mixed-signal, multi-language simulator for IC or PCB designs. It uses SPICE syntax for analog descriptions, Verilog-HDL and VHDL for digital, Verilog-A/AMS, VHDL-AMS and ABCD (a combination of SPICE and C) for analog behavioral, and C for DSP algorithms.

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Operating Systems
Implementation
Translations

Recent releases

  •  19 May 2014 09:00

    Release Notes: This release provides a number of minor fixes and enhancements, including HSPICE compatibility improvements, as well as Verilog and VHDL language compliance corrections.

    •  19 May 2014 08:57

      Release Notes: This release provides Imbalance Locate analysis using dispersion data in foundry models, an enhanced Sweep dialog for multiple parameter sweeping, an optimizer for multiple analysis optimizations, accelerated transient noise simulations with integrated transistor level multi-threading, improved back-annotation file for schematic editors, auto-completion for HDL languages based on templates, and integrated help with tooltip display of expected values and parameters for Verilog functions.

      •  19 May 2014 08:54

        Release Notes: This release provides a brand-new and efficient waveform viewer, for analysis of mixed-signal simulation results, as well as a styled user interface, enabling users to access and configure more easily the powerful analyses provided by the mixed-signal simulator. This release also integrates the standard BSIM SOI compact model for Silicon-On-Insulator circuit design.

        •  19 Feb 2013 16:43

          Release Notes: This release improves the loading runtime of large Verilog files with an important number of ports and implements support of the .MALIAS directive to assign an alias to a model or sub-circuit name, along with a number of minor corrections.

          •  19 Feb 2013 16:40

            Release Notes: This release implements nested sweeping, sweeping with two or more parameters at the same time, an improved the time step predictor to accelerate SPICE transient simulations, coverage analysis support for Verilog question-colon operator and for VHDL concurrent assignment statements, the SPICE model BSIM-CMG v106.1, and an optimizer targeting design of analog blocks.

            Recent comments

            03 Feb 2004 20:10 Wardini

            Mixed signal simulation
            My company has 3 licenses of SMASH. It works pretty good.

            If anyone wants to talk to me about it, look up my company SemQuest Inc. and I'll discuss it.

            Dave

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