TTA-based Co-design Environment (TCE) is a toolset that provides a complete co-design flow from C programs down to synthesizable VHDL and parallel program binaries. Processor customization points include the register files, function units, supported operations, and the interconnection network.
|Tags||Electronic Design Automation (EDA) Processor design VHDL Compilers Hardware|
|Operating Systems||Linux FreeBSD|
|Implementation||C++ C Python|
Release Notes: This release adds support for LLVM 3.4. OSAL operands now have widths and element counts, to support multiple size operations in the same function unit, among other things. Several bug fixes are also included.
Release Notes: This release adds support for LLVM 3.3, improved LLVM-side if-conversion, an initial operand sharing implementation, native support for half precision floats, several usability improvements to the Processor Designer GUI, bugfixes, and more.
Release Notes: This release adds support for LLVM 3.2, initial support for half-precision floats, improved vector support, and OpenCL host-tta-device mode simulation with pocl's ttasim driver.
Release Notes: This release adds support for LLVM 3.1, an experimental Verilog backend for the Processor Generator, support for explicit access to multiple address spaces from C, a simplified C++ interface for accessing the simulation engine, automated generation of clustered-style TTA machines, experimental vector input, and a bottom-up instruction scheduler.
Release Notes: This release includes support for LLVM 3.0, experimental OpenCL C Embedded Profile support (in offline compilation/standalone mode), a lightweight (debug output) printing library, support for calling custom operations in specific function units, generalizations to the architecture description format to allow using the instruction scheduler for operation triggered architectures (with a proof of concept for the Cell SPU), several code generator improvements, and plenty of bugfixes.